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Real-Time Concepts for Embedded SystemsThe device can continue to generate interrupts, but the processor ignores them. g Disable the global system-wide interrupt request line to the processor (the line between the PIC and the core processor), as exemplified in Figure 10.1. Interrupts of any priority level do not reach the processor. This step is equivalent to masking interrupts of the highest priority level. An ISR would typically deploy one of these three methods to disable interrupts for one or all of these reasons: g the ISR tries to reduce the total number of interrupts raised by the device, g the ISR is non-reentrant, and g the ISR needs to perform some atomic operations. Some processor architectures keep the information on which interrupts or interrupt levels are disabled inside the system status register. Other processor architectures use an interrupt mask register (IMR). Therefore, an ISR needs to save the current IMR onto the stack and disable interrupts according to its own requirements by setting new mask values into the IMR. The IMR only applies to maskable asynchronous exceptions and, therefore, is not saved by synchronous exception routines ...» |
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